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CDP1871A, CDP1871AC
REFERENCE APP NOTE 7374
August 1996
CMOS Keyboard Encoder
Description
The CDP1871A is a keyboard encoder designed to directly interface between a CDP1800-series microprocessor and a mechanical keyboard array, providing up to 53 ASCII coded keys and 32 HEX coded keys, as shown in the system diagram (Figure 1). The keyboard may consist of simple single-pole single-throw (SPST) mechanical switches. Inputs are provided for alpha-lock, control, and shift functions, allowing 160 unique codes. An external R-C input is available for user-selectable debounce times. The Nkey lock-out feature prevents unwanted key codes if two or more keys are pressed simultaneously. The CDP1871A and CDP1871AC are functionally identical. They differ in that the CDP1871A has a recommended operating voltage range of 4V to 10.5V, and the CDP1871AC has a recommended operating voltage range 4V to 6.5V. These types are supplied in 40 lead dual-in-line ceramic packages (D suffix), and 40 lead dual-in-line plastic packages (E suffix), and 44 lead plastic chip-carrier packages (Q suffix).
Features
* Directly Interfaces with CDP1800-Series Microprocessor * Low Power Dissipation * Three-State Outputs * Scans and Generates Code for 53 Key ASCII Keyboard Plus 32 HEX Keys (SPST Mechanical Contact Switches) * Shift, Control, and Alpha Lock Input * RC-Controlled Debounce Circuitry * Single Supply 4V to 10.5V . . . . . . . . . . . . . (CDP1871A) 4V to 6.5V . . . . . . . . . . . . . (CDP1871AC) * N-Key Lockout
Ordering Information
PACKAGE PDIP PLCC SBDIP Burn-In TEMP. RANGE 5V 10V PKG. NO.
-40oC to +85oC CDP1871ACE -40oC to +85oC CDP1871ACQ -40oC to +85oC CDP1871ACD CDP1871ACDX
CDP1871AE E40.6 N44.65
CDP1871AD D40.6 D40.6
Pinouts
CONTROL DEBOUNCE
40 LEAD PDIP, CERDIP TOP VIEW
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 S1 S2 S3 S4 S5 S6 S7 S8 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VDD SHIFT CONTROL ALPHA DEBOUNCE RTP TPB DA BUS 7 BUS 6 BUS 5 BUS 4 BUS 3 BUS 2 BUS 1 BUS 0 CS4 CS3 CS2 CS1
NC
44 LEAD PLCC (Q Suffix) TOP VIEW
SHIFT ALPHA
VDD
D4
D3
D2
6 D5 D6 D7 D8 D9 D10 D11 S1 S2 S3 S4 7 8 9 10 11 12 13 14 15 16 17
5
4
3
D1
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 RPT TPB DA BUS 7 BUS 6 BUS 5 BUS 4 BUS 3 BUS 2 BUS 1 NC
18 19 20 21 22 23 24 25 26 27 28 CS1 CS2 CS3 CS4 BUS 0 VSS NC S5 S6 S7 S8
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
1374.2
4-66
CDP1871A, CDP1871AC
VDD 100K 40 21 N0-N2 CONTROL 23 MRD TPB CDP1800-SERIES CPU 24 34 CS1, CS2, CS3 CS4 TPB CDP1871A VDD SHIFT 39 SHIFT 1 D1 UP TO 11 SETS OF 8 SWITCHES EACH 0.1F 36 DEBOUNCE 11 D11
CONTROL 38
CONTROL S1 S2 S3 S4 S5 S6 S7 S8 12 13 14 15 16 17 18 19
ALPHA LOCK 37 ALPHA NORMAL
BUS0-BUS7 8 BIT DATA BUS
BUS0-BUS7 25 32
FIGURE 1. TYPICAL CDP1800 SERIES MICROPROCESSOR SYSTEM USING THE CDP1871A
CS1 21 CS2 22 CS3 23 CS4 24 TPB 34
CS
SCAN CLOCK
THREE-STAGE SCAN COUNTER
FIVE-STAGE SCAN COUNTER
BUS ENABLE CONTROL LOGIC 25 BUS 0 C1-C3 KEY DETECT F/F DEBOUNCE 36 RN VDD VSS 40 20 THREE-STATE OUTPUT BUFFERS 32 BUS 7
VDD RX CX
C4-C8
DA 33 STATUS LATCHES RPT 35 RPD KEY DOWN DETECT 1 OF 8 MUX LATCH
RPD
II DECODER/ DRIVERS TO KEY BOARD
RPD
RPD
FROM KEY BOARD 12 SENSE LINES 19 1 DI
DRIVE LINES
11 DII
37
39
38 CONTROL
ALPHA SHIFT
FIGURE 2. CDP1871A BLOCK DIAGRAM
4-67
CDP1871A, CDP1871AC
Absolute Maximum Ratings
(All Voltages Referenced to VSS Terminal) CDP1871A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +11V CDP1871AC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +7V Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V DC Input Current, any One Input . . . . . . . . . . . . . . . . . . . . . . . . .10mA
Thermal Information
Thermal Resistance (Typical) JA (oC/W) JC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 60 N/A PLCC Package . . . . . . . . . . . . . . . . . . 50 N/A SBDIP Package . . . . . . . . . . . . . . . . . . 60 18 Device Dissipation Per Output Transistor TA = Full Package Temperature Range (All Package Types) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mW Operating Temperature Range (TA) Package Type D. . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Package Type E and Q . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range (TSTG) . . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) At distance 1/16 1/32 In. (1.59 0.79mm) from case for 10s max . . . . . . . . . . . . . . . . . . . . . . . . . . . . +265oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Recommended Operating Conditions
At TA = -40 to +85oC. For maximum reliability, operating conditions should be selected so that operation is always within the following ranges: LIMITS CDP1871AD, CDP1871AE CDP1871ACD, CDP1871ACE MIN 4 VSS MAX 6.5 VDD UNITS V V
PARAMETER Supply Voltage Range Recommended Input Voltage Range Clock Input Frequency, TPB (Keyboard Capacitance = 200 pF) fCL
VDD (V)
MIN 4 VSS
MAX 10.5 VDD
5 10
DC DC
0.4 0.8
DC -
0.4 -
MHz MHz
NOTE: 1. Printed-circuit board mount: 57mm x 57mm minimum area x 1.6mm thick G10 epoxy glass, or equivalent.
Static Electrical Specifications
At TA = -40 to +85oC, Unless Otherwise Specified CONDITIONS CDP1871AD CDP1871AE VO (V) VIN (V) 0.5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 VDD (V) 5 10 5 10 5 10 5 10 (NOTE 1) TYP 0.1 1 1 2 1.5 2 0.1 0.2 LIMITS CDP1871ACD CDP1871ACE (NOTE1) TYP 1 1 1.5 0.1 -
PARAMETER Quiescent Device Current IDD
MIN 0.5 1 0.75 1 0.05 0.1
MAX 50 200 -
MIN 0.5 0.75 0.05 -
MAX 200 -
UNITS A A mA mA mA mA mA mA
-
Output Low Drive (Sink) Current (Except Debounce and D1-D11) Debounce
IOL
0.4 0.5
IOL
0.4 0.5
D1-D11
IOL
0.4 0.5
4-68
CDP1871A, CDP1871ACCDP1871A, CDP1871AC
Static Electrical Specifications
At TA = -40 to +85oC, Unless Otherwise Specified (Continued) CONDITIONS CDP1871AD CDP1871AE VO (V) IOH 4.6 9.5 Input Low Voltage (Except Debounce) VIL 0.5, 4.5 1, 9 Input High Voltage (Except Debounce) VIH 0.5, 4.5 1, 9 Debounce Schmitt Trigger Input Voltage Positive Trigger Voltage Negative Trigger Voltage VN VD 0.4 VIN (V) 0, 5 0, 10 VDD (V) 5 10 5 10 5 10 5 (NOTE 1) TYP -0.6 -1.5 3.3 LIMITS CDP1871ACD CDP1871ACE (NOTE1) TYP -0.6 3.3
PARAMETER Output High Drive (Source) Current
MIN -0.3 -0.75 3.5 7 2.0
MAX 1.5 3 4.0
MIN -0.3 3.5 2.0
MAX 1.5 4.0
UNITS mA mA V V V V V
0.5 0.4 0.5
0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 0, 5 0, 10 -
10 5 10 5 10 5 10 5 10 5 10 5 10 -
4.0 0.8 1.9 0.3 0.7 4.95 9.95 7
6.3 1.8 4.0 1.6 2.3 0 0 5 10 0.01 0.01 0.01 0.02 14
8.0 3.0 6.0 2.6 4.7 0.05 0.05 1 1 1 2 24
0.8 0.3 4.95 7
1.8 1.6 0 5 0.01 0.02 14
3.0 2.6 0.05 1 2 24
V V V V V V V V V A A A A k
Hysteresis
VH
0.4 0.5
Output Voltage Low Level
VOL
-
Output Voltage High Level
VOH
-
Input Leakage Current (Except S1-S8, Shift, Control) Three-State Output Leakage Current
IIN
-
IOUT
0, 5 0, 10
Pull-Down Resistor Value (S1-S8, Shift, Control) Operating Current (All Outputs Unloaded) fCL = 0.4MHz fCL = 0.8MHz NOTE:
RPD
-
IOPER
0.5, 4.5 1, 9
0, 5 0, 10
5 10
-
0.6 2.7
-
-
0.6 -
-
mA mA
1. Typical values are for TA = +25oC and nominal VDD.
4-69
CDP1871A, CDP1871AC Functional Description of CDP1871A Terminals
D1 - D11 (Outputs): Drive lines for the 11 x 8 keyboard switch matrix. These outputs are connected through the external switch matrix to the sense lines (S1 - S8). S1 - S8 (Inputs): Sense lines for the 11 x 8 keyboard maxtrix. These inputs have internal pull-down resistors and are driven high by appropriate drive line when a keyboard switch is closed. CS1, CS2, CS3, CS4 (Inputs): Chip select inputs, which are used to enable the three-state data bus outputs (BUS 0 - BUS 7) and to enable the resetting of the status flag (DA), which occurs on the low-to-high transition of TPB. These four inputs are normally connected to the N-lines (N0-N2) and MRD output of the CDP1800series microprocessor. (Table 2) BUS 0 - BUS 7 (Outputs): Three-state data bus outputs which provide the ASCll and HEX codes of the detected keys. The outputs are normally connected to the BUS 0 - BUS 7 terminals of the CDP1800series microprocessor. DA (Output): The data available output flag which is set low when a valid key closure is detected. It is reset high by the low-to-high transition of TPB when data is read from the CDP1871A. This output is normally connected to a flag input (EF1 - EF4) of the CDP1800-series microprocessor. ALPHA, SHIFT, CONTROL (Inputs): A high on the SHIFT or CONTROL inputs will be internally latched (after the debounce time) and the drive and sense line decoding will be modified as shown in Table 3. They are normally connected to the keyboard, but produce no code by themselves. The SHIFT and CONTROL inputs have internal pull-down resistors to simplify use with momentary contact switches. The ALPHA input is not latched and is designed for a standard SPDT switch to provide an alpha-lock function. When ALPHA = 1 the drive and sense line decoding will be modified as shown in Table 3. VDD, VSS: VDD is the positive supply voltage input. VSS is the most negative supply voltage terminal and is normal connected to ground. All outputs swing from VSS to VDD. The recommended input voltage swing is from VSS to VDD.
TABLE 1. SWITCH INPUT FUNCTIONS CONTROL 0 1 0 0 NOTE: X = Don't Care SHIFT 0 X 1 0 ALPHA 0 X X 1 KEY FUNCTION Normal Control Shift Alpha
TPB (Input): The input clock used to drive the scan generator and reset the status flag (DA). This input is normally connected to the TPB output of the CDP1800-series microprocessor. RPT (Output): The repeat output flag which is used to indicate that a key is still closed after data has been read from the CDP1871A (DA = high). It remains low as long as the key is closed and is used for an autorepeat function, under CPU control. This output is normally connected to a flag input (EF1 - EF4) of the CDP1800-series microprocessor. DEBOUNCE (Input): This input is connected to the junction of an external resistor to VDD and capacitor to VSS. It provides a debounce time delay (t RC) after the release of a key. If a debounce is not desired, the external pull-up resistor is still required.
4-70
CDP1871A, CDP1871AC
TABLE 2. VALID N-LINE CONNECTIONS CDP1871A SIGNAL CPU CDP1800- Series Signal CS4 MRD MRD MRD CS3 N2 N0 N2 CS2 N0 N1 N1 CS1 N1 N2 N0 CPU INPUT INSTRUCTION INP5 INP3 INP6
TABLE 3. DRIVE AND SENSE LINE KEYBOARD CONNECTIONS (NOTE 2) DRIVE LINES SENSE LINES S1 SP 0 D1 0 ( 8 D2 8 ` @ D3 @ NUL H h D4 H BS P p D5 P DLE X x D6 X CA N Y EM Z SU B [ ES C \ Escape Line Feed D7 Space D8 801
6
D9 8816
D10 9016
D11 9816
S2
! 1
1
) 9
9
A a
A SOH B STX
I i J j
I HT J LF
Q q R r
Q DC1 R DC2
Y y Z z
811
6
8916
9116
9916
S3
" 2
2
* :
:
B b
821
6
8A16
9216
9A16
S4
# 3
3
+ ;
;
C c
C ETX
K k
K VT
S s
S DC3
{ [
831
6
8B16
9316
9B16
S5
$
4
<
,
D
D
L
L
T
T
| | \ } ]
841
6
8C16
9416
9C16
4 S6 % 5 5
, = -
d E e
EOT E ENQ
I M m
FF M CR
t U u
DC4 U NA K V SY N W ETB
FS ] GS RS Carriage Return 851
6
8D16
9516
9D16
S7
& 6
6
> .
.
F f
F ACK
N n
N SO
V v
~ Del -
861
6
8E16
9616
9E16
S8
` 7
7
? /
/
G g
G BEL
O o
O SI
W W
US
Delete
871
6
8F16
9716
9F16
SHIFT (Note 1) KEY: NORMAL NOTES:
ALPHA (Note 1) CONTROL (Note 1)
1. CONTROL overrides SHIFT and ALPHA
= No Response
2. Showing ASCII outputs for all combinations with and without SHIFT, ALPHA LOCK and CONTROL. 3. Drive lines 8, 9, 10 and 11 generate non-ASCII hex values which can be used for special codes.
4-71
CDP1871A, CDP1871AC
TABLE 4. HEXIDECIMAL VALUES OF ASCII CHARACTERS MSD b7 0 b6 BITS b5 HEX b4 0 0 0 0 0 0 0 0 LSD 1 1 1 1 1 b3 0 0 0 0 1 1 1 1 0 0 0 0 1 b2 0 0 1 1 0 0 1 1 0 0 1 1 0 b1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 2 3 4 5 6 7 8 9 A B C 0 NUL SOH STX ETX EOT ENQ ACK BEL BS HT LF VT FF 1 DLE DC1 DC2 DC3 DC4 NAK SYN ETB CAN EM SUB ESC FS 2 SP ! " # $ % & / ( ) * + , 3 0 1 2 3 4 5 6 7 8 9 : ; < 4 @ A B C D E F G H I J K L 5 P Q R S T U V W X Y Z [ \ 6 \ a b c d e f g h i j k l 7 p q r s t u v w x y z { | | } ~ DEL 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1
1 1 1
1 1 1
0 1 1
1 0 1
D E F
CR SO SI
GS RS US
. /
= > ?
M N O
] -
m n o
Operation
The CDP1871A is made up of two major sections: the counter/scan-selection logic and the control logic (Figure 2). The counter and scan-selection logic scans the keyboard array using the drive lines (D1-D11) and the sense lines (S1S8). The outputs of the internal 5-stage scancounter are conditionally encoded by the ALPHA, SHIFT, and CONTROL inputs (Table 1, Table 3) and are used to drive the D1-D11 output lines high one at a time. Each D1-D11 output may drive up to eight keys, which are sampled by the sense line inputs (S1-S8). The S1-S8 inputs are enabled by the internal 3-stage scancounter. The control logic interfaces with the CDP1800-series I/O and timing signals to establish timing and status conditions for the CDP1871A. The TPB input clocks the scancounters and is also used to reset the Data Available output (DA). When a valid keydown condition is detected on a sense line, the control logic inhibits the clock to the scancounters on the next low-to-high transition of TPB and the DA output is set low. The scancounter outputs (C1 - C8) represent the ASCII and HEX key codes and are used to drive the BUS 0 - BUS 7 outputs, which interface directly to the CDP1800-Series data bus. The BUS 0 - BUS 7 outputs, which are normally three-stated, are enabled by decoding the CS inputs during a CPU input instruction (Table 2). The low-to-high transition of TPB during the input instruction resets the DA output high. Once the DA output has been reset, it cannot go low again until the present key is released and a new keydown condition is detected. (This prevents unwanted repeated keycode outputs which may be caused by fast software routines). After the depressed key is released and the debounce delay (determined by RX, CX) has occurred, the scan clock inhibit is removed, allowing the scancounters to advance on the following high-to-low transitions of TPB. This provides an N-key lockout feature, which prevents the entry of erroneous codes when two or more keys are pressed simultaneously. The first key pressed in the scanning order is recognized, while all other keys pressed are ignored until the first key is released
4-72
CDP1871A, CDP1871AC
and read by the CPU, at which time the next key pressed in the scanning order is detected. If the first key remains closed after the CPU reads the data and resets the DA output, on the low-to-high transition of TPB, an auxiliary signal (RPT) is generated and is available to the CPU to indicate an autorepeat condition. The RPT output is reset high at the end of the debounce delay after the depressed key is released. The DEBOUNCE input provides a terminal connection for an external user-selected RC circuit to eliminate false detection of a keydown condition caused by keyboard noise. The operation of the DEBOUNCE circuit is shown in Figure 2 (Pin 36). When a valid keydown is detected, the on-chip activeresistor device (RN) is enabled and the external capacitor (CX) is discharged, providing a key closure debounce time RNCX. This discharge is sensed by the Schmitt-trigger inverter, which clocks the DA flip-flop (latching the DA output low and inhibiting the scan clock). (The DA F/F is reset by the low-to-high transition of TPB when the CS inputs are enabled). When a valid key-release is detected RN is disabled and CX begins to charge through the external resistor (RX), providing a key-release debounce time RXCX. This charge time is again sensed by the Schmitt-trigger inverter, enabling the scan clock to continue on the next high-to-low transitions of TPB, after the current keycode data is read by the CPU.
Dynamic Electrical Specifications
At TA = -40 to +85oC, VDD 5%, Unless Otherwise Specified LIMITS CDP1871AD, CDP1871AE CDP1871ACD, CDP1871ACE (NOTE 1) TYP 40 260 70 850 120 100 150 350 -
PARAMETER Clock Cycle Time tCC
VDD (V) 5 10
MIN 100 50 -
(NOTE 1) TYP 40 20 260 130 70 35 850 425 120 60 100 50 150 75 350 170
MAX 500 250 150 75 1900 950 250 125 200 100 400 200 700 350
MIN 100 -
MAX 500 150 1900 250 200 400 700 -
UNITS Note 2 Note 2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Clock Pulse Width High
tCWH
5 10
Data Available Valid Delay
tDAL
5 10
Data Available Invalid Delay
tDAH
5 10
Scan Count Delay (Non-Repeat)
tCD1
5 10
Data Out Valid Delay
tCDV
5 10
Data Out Hold Time
tCDH
5 10
Repeat Valid Delay
tRPL
5 10
Repeat Invalid Delay
tRPH
5 10
NOTES: 1. Typical values are for TA = +25oC and nominal VDD. 2. tCC = tCWH + tCWL tCWL = tCD1 + KC k = 0.9ns per pF c = Keyboard capacitance (pF)
4-73
CDP1871A, CDP1871AC
tCC TPB tCWH tCWL
KEY CLOSURE tDAL DA
CLOSED
OPEN tDAH
RPT RNCX RXCX
DEBOUNCE tCD1 D1-D11 PRESENT COUNT NEXT COUNT
CS (NOTE) tCDV BUS0-BUS7 NOTE: CS = CS1 * CS2 * CS3 * CS4 CS1, CS2, CS3 = (CPU N-LINES) CS4 (MRD) is High for CPU Input Instruction VALID tCDH
FIGURE 3. CDP1871A DYNAMIC TIMING DIAGRAM (NON-REPEAT)
TPB
KEY DEPRESSED
CLOSED tDAH
OPEN
DA tRPH RPT tRPL
RXCX DEBOUNCE
D1-D11
PRESENT COUNT
NEXT COUNT
CS (NOTE) tCDV BUS0-BUS7 VALID tCDH
NOTE: CS = CS1 * CS2 * CS3 * CS4 CS1, CS2, CS3 = (CPU N-LINES) CS4 (MRD) is High for CPU Input Instruction
FIGURE 4. FIGURE 4. CDP1871A DYNAMIC TIMING DIAGRAM (REPEAT)
4-74
CDP1871A, CDP1871AC
START MAIN PROGRAM
N
DA =0? Y INPUT KEY DATA STORE KEY DATA
DATA = ASCII CTRL CHAR. OR HEX CODE ? Y
N
DISPLAY CHARACTER
PERFORM CONTROL FUNCTION
N
IS CHAR. A REPEATABLE CHAR. ? Y DELAY
Y
RPT =0? N
FIGURE 5. TYPICAL SYSTEM SOFTWARE FLOWCHART FOR CDP1871A, CDP1871AC
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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4-75

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